Program organization directives in 8086

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Source Index SI is a 16-bit register. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register BX or BP and index register SI or DI , the resulting value is a pointer to location where data resides.. Here I'll write some pseudocode assembly. This is a type 1 interrupt.

It has BHE bar signal on pin no. It is more complex because it can be unconditional or conditional on the result of some previous operations or on flag value. This hampers the ability to access any arbitrary location in memory, effectively making it a two step operation - load the segment register - then access the offset address. Memory segmentation is an attempt to address more memory than the processor architecture would normally allow. It needs one IC 74343 for de-multiplexing AD 0 -AD 7.. This may put a limitation on the maximum time delay that can be generated using the above delay subroutine.

Stack memory can be placed anywhere in memory. Interrupt is processed in the same way as the INTR interrupt. CS register cannot be changed directly.

Articles Details - Auxiliary carry Flag AF - set if there was a carry from or borrow to bits 0-3 in the AL register.

They can be used as four 16 bit registers AX, BX, CX, and DX. There are four 16 bit segment registers, CS code segment , DS data segment , SS stack segment , and ES extra segment. There is the 16 bit instruction pointer, IP, and there is a 16 bit flags register. Memory Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Data memory - the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB if all four segments point to different 64 KB blocks. Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: some registers and instructions by default may use the ES or SS segments instead of DS segment. Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. Each interrupt vector is a 32-bit pointer in format segment:offset. FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. Interrupts The processor has the following interrupts: INTR is a maskable hardware interrupt. Interrupt processing routine should return with the IRET instruction. NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i. This interrupt has higher priority then the maskable interrupt. Software interrupts can be caused by:. INT instruction - breakpoint interrupt. This is a type 3 interrupt. INT instruction - any one interrupt from available 256 interrupts. INTO instruction - interrupt on overflow. Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. Processor exceptions: divide error type 0 , unused opcode type 6 and escape opcode type 7. Software interrupt processing is the same as for the hardware interrupts. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment CS is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer IP register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment SS is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer SP and base pointer BP registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment DS is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers AX, BX, CX, DX and index register SI, DI is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment ES is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. The following registers are both general and index registers: Stack Pointer SP is a 16-bit register pointing to program stack. Base Pointer BP is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index SI is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index DI is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: Instruction Pointer IP is a 16-bit register. Flags is a 16-bit register containing 9 1-bit flags:. Overflow Flag OF - set if the result is too large positive number, or is too small negative number to fit into destination operand. Direction Flag DF - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag IF - setting this bit enables maskable interrupts. Single-step Flag TF - if set then single-step interrupt will occur after the next instruction. Sign Flag SF - set if the most significant bit of the result is set. Zero Flag ZF - set if the result is zero. Auxiliary carry Flag AF - set if there was a carry from or borrow to bits 0-3 in the AL register. Carry Flag CF - set if there was a carry from or borrow to the most significant bit during last result calculation. Instruction Set 8086 instruction set consists of the following instructions:. Control transfer - conditional, unconditional, call subroutine and return from subroutine. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Based - 8-bit or 16-bit instruction operand is added to the contents of a base register BX or BP , the resulting value is a pointer to location where data resides. Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register SI or DI , the resulting value is a pointer to location where data resides. Based Indexed - the contents of a base register BX or BP is added to the contents of an index register SI or DI , the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register BX or BP and index register SI or DI , the resulting value is a pointer to location where data resides. Segmented addressing probably originated with Burroughs. Suppose you have a flat memory model, and a program starting at location 4000. Here I'll write some pseudocode assembly. The other address is part of a branch, and probably stored as a relative offset. Suppose we store this code on disk, and then later we read it in. If we read it in starting at location 4000h, we are fine. If we read it in elsewhere, we might have a problem. Now suppose we have a timeshare system, and we want to page programs in and out, and manage memory for the system. We have a problem; we have to correct all the addresses of a program when it is read in. And we can't do that. How do we detect a jump table and correct the address? I might do this by taking a value and shifting it a few places. For example, I might have a lookup table for the sine of angles. The sine of angle X is stored as a four-byte floating-point value, starting at location 2000h. They are modified automatically by CPU aftermathematical operations and allow one to determine the type of theresult as well as determine conditions to transfer control to otherparts of the program. Generally you cannot access these registers directly. Carry Flag CF - this flag is set to 1 whenthere is an unsigned overflow. For example when you addbytes 255 + 1 result is not in range 0... When thereis no overflow this flag is set to 0. Parity Flag PF - this flag is set to 1 whenthere is even number of one bits in result, and to 0 whenthere is odd number of one bits. Auxiliary Flag AF - set to 1 when there is an unsigned overflow for low nibble 4 bits. Zero Flag ZF - set to 1 when result is zero. For non-zero result this flag is set to 0. Sign Flag SF - set to 1 when result is negative. When result is positive it is set to 0. This flag takes the value of the most significant bit. Trap Flag TF - Used for on-chip debugging. Interrupt enable Flag IF - when this flag is set to 1 CPU reacts to interrupts from external devices. Direction Flag DF - this flag is used by someinstructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the processing is done backward. Overflow Flag OF - set to 1 when there is a signed overflow. For example, when you add bytes 100 +50 result is not in range -128... Code segment CS is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer IP register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.. Data segment DS is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers AX, BX, CX, DX and index register SI, DI is located in the data segment. DS register can be changed directly using POP and LDS instructions.. Code segment CS is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer IP register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.. Data segment DS is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers AX, BX, CX, DX and index register SI, DI is located in the data segment. DS register can be changed directly using POP and LDS instructions. In the 8086 microprocessor, the Code Segment CS register contains the paragraph address that will be added to the Instruction Pointer to obtain the address of the next instruction. Similarly, the Data Segment DS register contains the paragraph address that will be added to the Effective Address that is computed to find the address of the data used by that instruction. There are segment override prefixes, but the default use is CS for instructions and DS for data. Using segment registers to select a 'bank of memory' the CPU can use much more 20 bit addressing space Memory Program, data and stack memories occupy the same memory space. The total addressable memory size is 1MB. As the most of the processor instructions use 16-bit pointers the processor can effectively address only 64 KB of memory. Jump and call instructions can be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jump within approximately +127 - -127 bytes from current instruction. Data memory - the processor can access data in any one out of 4 available segments, which limits the size of accessible memory to 256 KB if all four segments point to different 64 KB blocks. Accessing data from the Data, Code, Stack or Extra segments can be usually done by prefixing instructions with the DS:, CS:, SS: or ES: some registers and instructions by default may use the ES or SS segments instead of DS segment. Word data can be located at odd or even byte boundaries. The processor uses two memory accesses to read 16-bit word located at odd byte boundaries. Reading word data from even byte boundaries requires only one memory access. Stack memory can be placed anywhere in memory. Each interrupt vector is a 32-bit pointer in format segment:offset. FFFF0h - FFFFFh - after RESET the processor always starts program execution at the FFFF0h address. Interrupts The processor has the following interrupts: INTR is a maskable hardware interrupt. Interrupt processing routine should return with the IRET instruction. NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i. This interrupt has higher priority then the maskable interrupt. Software interrupts can be caused by:. INT instruction - breakpoint interrupt. This is a type 3 interrupt. INT instruction - any one interrupt from available 256 interrupts. INTO instruction - interrupt on overflow. Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine. Processor exceptions: divide error type 0 , unused opcode type 6 and escape opcode type 7. Software interrupt processing is the same as for the hardware interrupts. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers: Code segment CS is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer IP register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions. Stack segment SS is a 16-bit register containing address of 64KB segment with program stack. By default, the processor assumes that all data referenced by the stack pointer SP and base pointer BP registers is located in the stack segment. SS register can be changed directly using POP instruction. Data segment DS is a 16-bit register containing address of 64KB segment with program data. By default, the processor assumes that all data referenced by general registers AX, BX, CX, DX and index register SI, DI is located in the data segment. DS register can be changed directly using POP and LDS instructions. Extra segment ES is a 16-bit register containing address of 64KB segment, usually with program data. By default, the processor assumes that the DI register references the ES segment in string manipulation instructions. ES register can be changed directly using POP and LES instructions. It is possible to change default segments used by general and index registers by prefixing instructions with a CS, SS, DS or ES prefix. All general registers of the 8086 microprocessor can be used for arithmetic and logic operations. The general registers are: Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AH contains the high-order byte. Base register consists of 2 8-bit registers BL and BH, which can be combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the high-order byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing. Count register consists of 2 8-bit registers CL and CH, which can be combined together and used as a 16-bit register CX. When combined, CL register contains the low-order byte of the word, and CH contains the high-order byte. Data register consists of 2 8-bit registers DL and DH, which can be combined together and used as a 16-bit register DX. When combined, DL register contains the low-order byte of the word, and DH contains the high-order byte. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number. The following registers are both general and index registers: Stack Pointer SP is a 16-bit register pointing to program stack. Base Pointer BP is a 16-bit register pointing to data in stack segment. BP register is usually used for based, based indexed or register indirect addressing. Source Index SI is a 16-bit register. SI is used for indexed, based indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Destination Index DI is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. Other registers: Instruction Pointer IP is a 16-bit register. Flags is a 16-bit register containing 9 1-bit flags:. Overflow Flag OF - set if the result is too large positive number, or is too small negative number to fit into destination operand. Direction Flag DF - if set then string manipulation instructions will auto-decrement index registers. If cleared then the index registers will be auto-incremented. Interrupt-enable Flag IF - setting this bit enables maskable interrupts. Single-step Flag TF - if set then single-step interrupt will occur after the next instruction. Sign Flag SF - set if the most significant bit of the result is set. Zero Flag ZF - set if the result is zero. Auxiliary carry Flag AF - set if there was a carry from or borrow to bits 0-3 in the AL register. Carry Flag CF - set if there was a carry from or borrow to the most significant bit during last result calculation. Instruction Set 8086 instruction set consists of the following instructions:. Control transfer - conditional, unconditional, call subroutine and return from subroutine. Register - references the data in a register or in a register pair. Immediate - the data is provided in the instruction. Direct - the instruction operand specifies the memory address where data is located. Register indirect - instruction specifies a register containing an address, where data is located. This addressing mode works with SI, DI, BX and BP registers. Based - 8-bit or 16-bit instruction operand is added to the contents of a base register BX or BP , the resulting value is a pointer to location where data resides. Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register SI or DI , the resulting value is a pointer to location where data resides. Based Indexed - the contents of a base register BX or BP is added to the contents of an index register SI or DI , the resulting value is a pointer to location where data resides. Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contents of a base register BX or BP and index register SI or DI , the resulting value is a pointer to location where data resides.. There are some registers that also serve as general purpose registers. The 8086 machine contains of four 16-bit data registers that are accessible on a byte or 16-bit basis. It also has four 16-bit pointers and index registers. The data registers can be used as general purpose registers in some instructions. In others registers are used implicitly. For example: A multiply instruction always uses accumulator. The four pointer registers each with segment offset are also used in a number of operations implicitly. There are also four segment registers. Three of these segment registers are used in a dedicated, implicit way to point to the segment of the current instruction, a segment containing data and a segment containing a stack. This type of structure is useful in branch operations. The dedicated and implicit uses provide for compact encoding at the cost of reduced flexibility. The 8086 also includes an instruction pointer and a set of 1 bit status and control flags. The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register. The instruction Queue is 6 byte long. The instruction Queue is 4 byte long. In 8086 memory divides into two banks, up to 1,048,576 bytes. The memory in 8088 does not divide in to two banks as 8086. The data bus of 8086 is 16-bit wide. The data bus of 8088 is 8-bit wide. It has BHE bar signal on pin no. It does not has BHE bar signal on pin no. It has no S7 pin. In 8088, address bus, AD 7 - AD 0 buses are multiplexed. It needs two IC 74343 for de-multiplexing AD 0 -AD 19. It needs one IC 74343 for de-multiplexing AD 0 -AD 7.. Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 Explain the register organization of Intel 8086 The Microprocessor 8086 is a 16-bit CPU available in differentclock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessorconfiguration to achieve high performance. The pins serve aparticular function in minimum mode single processor mode andother function in maximum mode configuration multiprocessor mode. The 8086 signals can be categorised in three groups. The first are the signal having common functions in minimum as wellas maximum mode. The second are the signals which have special functions for minimummode The third are the signals having special functions for maximummode. The following signal descriptions are common for both modes. Address remains on the lines during T1 state, while the data isavailable on the data bus during T2, T3, Tw and T4. These lines areactive high and float to a tristate during interrupt acknowledgeand local bus hold acknowledge cycles. Memory segmentation is an attempt to address more memory than the processor architecture would normally allow. What Intel did was provide four more registers called segment registers which would provide the base address of an address in physical memory to which the processor generated effective address would be added. The segment register is still 16 bits in size, but it is left shifted by four before being added to the effective address. This creates a physical address that is 20 bits in size, for a total address range of 1 mb. Note that you are still constrained to a segment size of 64 kb, in that you must stay within 64 kb unless you intend to change the value of one of the segment registers. This hampers the ability to access any arbitrary location in memory, effectively making it a two step operation - load the segment register - then access the offset address. All opcode access is from CS. Default data access is from DS, unless a segment prefix is applied. All stack operations are from SS. Certain repeated string operations take place between DS and ES. Because of the segmented architecture, the concept of near and far grew up with the original PC and DOS and Windows. Basically, a near address was a 16 bit address that assumed the current segment, while a far address was a 32 bit address that contained both a segment and an offset. Note that the concept of a flat 32 bit address did not come into full play until true 32 bit operating systems hit the street, and that did not occur until the introduction of the 80386.